differentiate b/w RISC n CISC according to their instruction size and hardware, software? 5 marks.
find total capacity of hard disk.
find total capacity of hard disk.
5 marks.
A hard disk with 5 platters has 1024 tracks per platter,512 sectors
per track and 512 bytes/sector. What is the total capacity of the
disk?
Total bytes in each track= bytes per sector x total number of sectors
512 bytes x 512 sectors=0.2MB/track
Total bytes in each platter=
0.2MB x 1024 tracks=0.2GB/platter
Total capacity HDD= 5 x 0.2=1GB
what is the function of Control unit? 3 marks.
It is the unit that initiates sequences of micro operations. Control functions specify that a microoperation are binary variables. If it is in one state then corresponding microoperation is executed and in opposite state does not change the position of registers in the system. The active state of control variable can be either 1 or zero depending upon the application.
The control unit is responsible for generating control signals as well as the timing signals. Hence the control unit is responsible for the synchronization of internal as well as external events. By means of the control signals, the control unit instructs the data path what to do in every clock cycle during the execution of instructions.
what is the difference between control unit n data path? 2 marks
what is the difference between control unit n data path? 2 marks
The data path is the arithmetic portion of the Von Neumann architecture. It consists of registers, internal buses, arithmetic units and shifters.
what is the working of DMA controller? 5 marks
what is the working of DMA controller? 5 marks
What is DMA CONTROLLER?
“A DMA controller could be a CPU in itself and it could control the total activity and synchronize the transfer of data”. DMA could be considered as a technique of transferring data from I/O to memory and from memory to I/O without the intervention of the CPU. The CPU just sets up an I/O module or a memory subsystem, so that it passes control and the data could be passed on from I/O to memory or from memory to I/O or within the memory from one subsystem to another subsystem without interaction of the CPU. After this data transfer is complete, the control is passed from I/O back to the CPU.
define 64K x 1 static RAM chip? 5 marks.
The cell array is indicated as 256 × 256. So, there would be 256 rows and 256 columns. A 64k × 1 cell array requires 16 address lines, a read/write line,
, a chip select line, CS, and only a single data line. The lower order 8-address lines select one of the 256 rows using an 8-to-256 line row decoder. Thus the selected row contains 256 bits. The higher order 8-address lines select one of those 256 bits. The 256 bits in the row selected flow through a 256-to-1 line multiplexer on a read. On a memory write, the incoming bit flows through a 1-to-256 line demultiplexer that selects the correct column of the 256 possible columns.
Define RAID 0
Redundant Array of Independent Disks Mode 0) A popular disk subsystem that increases performance by interleaving data across two or more drives. Data are broken into blocks, called "stripes," and alternately written to two or more drives simultaneously to increase speed. For example, stripe 1 is written to drive 1 at the same time stripe 2 is written to drive 2. Then stripes 3 and 4 are written to drives 1 and 2 simultaneously and so on. When reading, stripes 1 and 2 are read simultaneously; then stripes 3 and 4 and so on.
Ironically, RAID 0 is a misnomer because there is nothing "redundant." If one drive fails, the entire RAID array fails. See disk striping, RAID 3, RAID 5 and RAID.
Calculate bandwidth
Ironically, RAID 0 is a misnomer because there is nothing "redundant." If one drive fails, the entire RAID array fails. See disk striping, RAID 3, RAID 5 and RAID.
Calculate bandwidth
Find the bandwidth of a memory system that has a latency of 25ns, a pre charge time of
5ns and transfers 2 bytes of data per access.
Solution
Time between two memory references
=latency + pre charge time
= 25 ns+ 5ns
= 30ns
Throughput = 1/30ns
7
=3.33x10
operations/second
7
Bandwidth = 2x 3.33x10
7
= 6.66x10
bytes/s
Discuss problems of Pipelining
Certain complications may arise from pipelining a processor. They are explained below:
Discuss problems of Pipelining
Certain complications may arise from pipelining a processor. They are explained below:
Data dependence
This refers to the situation when an instruction in one stage of the pipeline uses the results of an instruction in the previous stage. As an example let us consider the following two instructions …
S1: add r3, r2, r1
S2: sub r4, r5, r3
…
There is a data-dependence among the above two instructions. The register R3 is being written to in the instruction S1, while it is being read from in the instruction S2. If the instruction S2 is executed before instruction S1 is completed, it would result in an incorrect value of R3 being used.
Resolving the dependency
There are two methods to remedy this situation:
1. Pipeline stalls
These are inserted into the pipeline to block instructions from entering the pipeline until some instructions in the later part of the pipeline have completed execution. Hence our modified code would become
…
S1: add r3, r2, r1
6
stall
stall
stall
S2: sub r4, r5, r3
…
2. Data forwarding
When using data forwarding, special hardware is added to the processor, which allowsthe results of a particular pipeline stage to be transferred directly to another stage in the pipeline where they are required. Data may be forwarded directly from the execute stage of one instruction to the decode stage of the next instruction. Considering the above example, S1 will be in the execute stage when S2 will be decoded. Using a comparator we can determine that the destination operand of S1 and source operand of S2 are the same. So, the result of S1 may be directly forwarded to the decode stage.
Other complications include the “branch delay” and the “load delay”. These are
explained below:
Branch delay
Branches can cause problems for pipelined processors. It is difficult to predict whether a branch will be taken or not before the branch condition is tested. Hence if we treat a branch instruction like any normal instruction, the instructions following the branch will be loaded in the stages following the stage which carries the branch instruction. If the branch is taken, then those instructions would need to be removed from the pipeline and their effects if any, will have to be undone. An alternate method is to introduce stalls, or nop instructions, after the branch instruction.
Load delay
Another problem surfaces when a value is loaded into a register and then immediately used in the next operation. Consider the following example:
…
S1: load r2, 34(r1)
S2: add r5, r2, r3
…
In the above code, the “correct” value of R2 will be available after the memory access stage in the instruction S1. Hence even with data forwarding a stall will need to be placed between S1 and S2, so that S2 fetches its operands only after the memory access for S1 has been made.
Differenciate Shared Medium and Switched Medium
Shared Medium
If a number of computers are connected with a single physical medium (i.e. coaxial or fiber), this situation is called shared medium. Because of many computers, collision takes place and affects the data transfer rate. As the number of machines on a physical medium increases, the data transfer rate decreases.
Switched Medium
To increase the throughput, a switched medium is used.
R[ra] = R[rb] - R[rc] Discuss its functionality
Serial and Parallel data transfer
Cache Direct Memory access approach
2 marks questions
How you define microprogramming
Interrupt driven I/O
In Bus topology if we change bus to switch then what will happen
MCQ
RAID related 4-5
ISR related
An interrupt is a request to the CPU to suspend normal processing and temporarily divert the flow of control through a new program. This new program to which control is transferred is called an Interrupt Service Routine or ISR. Another name for an ISR is an Interrupt Handler.
Interrupt driven I/O 2-3
Interrupt driven I/O 2-3
Cache 2-3
RISC and CISC 2
Today is my paper
52 total question
40 one no mcq
what is ISA, explain ? 5 marks
how instruction set is defined 5 marks
one numircal 2 marks?
mostly mcq from the old papers........about 60%
52 total question
40 one no mcq
what is ISA, explain ? 5 marks
how instruction set is defined 5 marks
one numircal 2 marks?
mostly mcq from the old papers........about 60%
Read more: CS501 Current Final Term Papers Fall 2010 (11~26 Feb 2011) - Virtual University of Pakistan http://www.vustudents.net/group/cs501advancecomputerarchitecture/forum/topics/cs501-current-final-term#ixzz1EKnN82QL
Q1) suppose an I/O system with a single disk gets (on average) 200 I/O request/second. Assume that average time for a disk to service an I/O request is 4ms. What is the utilization time? 3Marks
Time for an I/O request = 4ms
=0.004sec
Server utilization = 200 x 0.004
= 0.8
Q2) Give an example when DMA can be brought into use? 3Marks
Q3) convert the hexadecimal number B316 to base 10
Q2) Give an example when DMA can be brought into use? 3Marks
Q3) convert the hexadecimal number B316 to base 10
5Marks
X=0
X= x+B (=11) =11
X=16*11+3= 179
Hence (B3)16 =(179)10
Q4) Does DMA affects the relationship b/w the memory system and CPU system. Explain with example.
5Marks
Q5) consider a 128kb direct mapping with a line length of 32 bytes
Determine the number of bits in the address that refers to the bytes within the cache
Determine the number of bits in the address required to select the cache line. 5Marks
Q6) consider the following floating point’s numbers 3 marks
-0.5 X 10-3
Find out the sign, significant and exponent
-0.5 × 10-3
Sign = -1
Significand= 0.5
Exponent= -3
Base = 10= fixed for given type of representation
Q7) why we represent sometime some numbers in sign magnitude form.
Where TCP/IP protocol is used?
Internet uses TCP/IP protocol. In the TCP/IP model, session and presentation layers are not present, so Store-Forward routing is used.
What do you know about DMA controller? 2
How can overflow occur in floating point representation?
What do you know about DMA controller? 2
How can overflow occur in floating point representation?
Overflow occurs when the exponent is too large and can not be represented in the
exponent field.
Explain a 4x8 memory cell array (2D)
Explain a 4x8 memory cell array (2D)
In this arrangement, 4×8 memory cell array is arranged in 2-dimensions. At the input, we have a 2×4 decoder. Two address bits at the input A0 and A1 would be decoded into 4 signal specifies select lines. The decoder selects one of four rows of cells and then whether the row will be read or written.
What is the meaning of ISA? Describe briefly 3
What is the meaning of ISA? Describe briefly 3
It means Instruction set Architecture.It defines the function of each instruction. The emphasis is on the behavior of the system rather than the hardware structure of the system.
What steps are involved in the response of a nested interrupt handler? 3
Explain the direct cache strategy.
What steps are involved in the response of a nested interrupt handler? 3
Explain the direct cache strategy.
In this technique, a particular block of data from main memory can be placed in only one location into the cache memory. It relies on principle of locality.
Cache address is composed of two fields:
• Group field
• Word field
Valid bit specifies that the information in the selected block is valid
Consider a 128KB direct-mapped cache with a line length of 32 bytes. 5
a. Determine the number of bits in the address that refer to the byte within a cache
line.
b. Determine the number of bits in the address required to select the cache line.
What do you under stand by RAID 0? Write down three features.
Consider a 128KB direct-mapped cache with a line length of 32 bytes. 5
a. Determine the number of bits in the address that refer to the byte within a cache
line.
b. Determine the number of bits in the address required to select the cache line.
What do you under stand by RAID 0? Write down three features.
Read more: CS501 Current All Final Term Spring 2010 Papers(August 2010) in This Discussion - Virtual University of Pakistan http://www.vustudents.net/group/cs408humancomputerinteraction/forum/topics/cs501-current-all-final-term?commentId=3783342%3AComment%3A194878&groupId=3783342%3AGroup%3A59491#ixzz1EKvRXxmb
1. FINALTERM EXAMINATION
Spring 2009
CS501- Advance Computer Architecture
Spring 2009
CS501- Advance Computer Architecture
Marks: 75
Question No: 1 ( Marks: 1 ) - Please choose one
Which one of the following is the memory organization of SRC processor?
o 2(8) * 8 bits
o 2(16) * 8 bits
o 232 * 8 bits
o 2(64) * 8 bits
Question No: 2 ( Marks: 1 ) - Please choose one
Type A format of SRC uses -----------instructions
o two
o three
o four
o five
Question No: 3 ( Marks: 1 ) - Please choose one
The instruction ---------------will load
the register R3 with the contents of the memory
location M [PC+56]
o Add R3, 56
o lar R3, 56
o ldr R3, 56
o str R3, 56
Question No: 4 ( Marks: 1 ) - Please choose one
Which format of the instruction is called the accumulator?
o 3-address instructions
o 2-address instructions
o 1-address instructions
o 0-address instructions
Question No: 5 ( Marks: 1 ) - Please choose one
Which one of the following are the code size
and the Number of memory
bytes respectively for a 2-address instruction?
o 4 bytes, 7 bytes
o 7 bytes, 16 bytes
o 10 bytes, 19 bytes
o 13 bytes, 22 bytes
2. Question No: 6 ( Marks: 1 ) - Please choose one
Which operator is used to name registers, or part of registers, in the Register
Transfer Language?
Which operator is used to name registers, or part of registers, in the Register
Transfer Language?
o :=
o &
o %
o ©
Question No: 7 ( Marks: 1 ) - Please choose one
The transmission of data in which each character is self-contained units with its
own start and stop bits is -----------
o Asynchronous
o Synchronous
o Parallel
o All of the given options
Question No: 8 ( Marks: 1 ) - Please choose one
Circuitry that is used to move data is called -------------
o Bus
o Port
o Disk
o Memory
Question No: 9 ( Marks: 1 ) - Please choose one
Which one of the following is NOT a technique used when the CPU wants to
exchange data with a peripheral device?
o Direct Memory Access (DMA).
o Interrupt driven I/O
o Programmed I/O
o Virtual Memory
Question No: 10 ( Marks: 1 ) - Please choose one
Every time you press a key, an interrupt is generated.
This is an example of
o Hardware interrupt
o Software interrupt
o Exception
o All of the given
Question No: 11 ( Marks: 1 ) - Please choose one
The interrupts which are pre-programmed and the processor automatically finds
the address of the ISR using interrupt vector table are
o Maskable
o Non-maskable
o Non-vectored
o Vectored
Question No: 12 ( Marks: 1 ) - Please choose one
Which is the last instruction of the ISR that is to be executed when the ISR
terminates?
o IRET
o IRQ
o INT
o NMI
Question No: 13 ( Marks: 1 ) - Please choose one
If NMI (non maskable intrupt) and INTR both interrupts occur simultaneously, then which one has the
precedence over the other.
o NMI
o INTR
o IRET
o All of the given
Question No: 14 ( Marks: 1 ) - Please choose one
Identify the following type of serial communication error condition:
The prior character that was received was not still read by the CPU and is
over written by a new received character.
o Framing error
o Parity error
o Overrun error
o Under-run error
Question No: 15 ( Marks: 1 ) - Please choose one
----------the device usually means reading its status register every so often until
the device's status changes to indicate that it has completed the request.
o Executing
o Interrupting
o Masking
o Polling
Question No: 16 ( Marks: 1 ) - Please choose one
Which I/O technique will be used by a sound card that may need to access data
stored in the computer's RAM?
o Programmed I/O
o Interrupt driven I/O
o Direct memory access(DMA)
o Polling
Question No: 17 ( Marks: 1 ) - Please choose one
For increased and better performance we use _____ which are usually made of glass.
o Coaxial Cables
o Twisted Pair Cables
o Fiber Optic Cables
o Shielded Twisted Pair Cables
Question No: 18 ( Marks: 1 ) - Please choose one
In _____ if we find some call party busy we can have provision of call waiting.
o Delay System
o Loss System
o Single Server Model
o None of the given
Question No: 19 ( Marks: 1 ) - Please choose one
In ____ technique memory is divided into segments of variable sizes depending upon
the requirements.
o Paging
o Segmentation
o Fragmentation
o None of the given
Question No: 20 ( Marks: 1 ) - Please choose one
For a request of data if the requested data is not present in the cache, it is called a _____
o Cache Miss
o Spatial Locality
o Temporal Locality
o Cache Hit
Question No: 21 ( Marks: 1 ) - Please choose one
An entire _____ memory can be erased in one or a few seconds which is much faster
than EPROM.
o PROM
o Cache
o EEPROM
o Flash Memory
Question No: 22 ( Marks: 1 ) - Please choose one
________chips have quartz windows and by applying ultraviolet light data can be
erased from them.
o PROM
o Flash Memory
o EPROM
o EEPROM
Question No: 23 ( Marks: 1 ) - Please choose one
The _______signal coming from the CPU tells the memory that some interaction is required between the CPU and memory.
o REQUEST
o COMPLETE
o None of the given
Question No: 24 ( Marks: 1 ) - Please choose one
______ is a combination of arithmetic, logic and shifter unit along with some
multiplexers and control unit.
o Barrel Rotator
o Control Unit
o Flip Flop
o ALU
Question No: 25 ( Marks: 1 ) - Please choose one
1. In Multiple Interrupt Line, a number of interrupt lines are provided between the
____________________ module.
o CPU and the I/O
o CPU and Memory
o Memory and I/O
o None of the given
Question No: 26 ( Marks: 1 ) - Please choose one
The data movement instructions ___________ data within the machine and to
or from input/output devices.
o Store
o Load
o Move
o None of given
Question No: 27 ( Marks: 1 ) - Please choose one
CRC has ------------ overhead as compared to Hamming code.
o Equal
o Greater
o Lesser
o None of the given
Question No: 28 ( Marks: 1 ) - Please choose one
The ________ is w-bit wide and contains a data word, directly connected to the data
bus which is b-bit wide memory address register (MAR) .
o Instruction Register(IR)
o memory address register (MAR)
o memory Buffer Register(MBR)
o Program counter (PC)
Question No: 29 ( Marks: 1 ) - Please choose one
In_______technique, a particular block of data from main memory can be placed in
only one location into the cache memory .
o Set Associative Mapping
o Direct Mapping
o Associative Mapping
o Block Placement
Question No: 30 ( Marks: 1 ) - Please choose one
_______ indicate the availability of page in main memory.
o Access Control Bits
o Used Bits
o Presence Bits
o None of the given
Question No: 31 ( Marks: 1 )
What are the hardware interrupts in a computer system?Mention its utility.
Question No: 32 ( Marks: 1 )
Consider a LAN, using bus topology. If we replace the bus with a switch, what change
will occur in such a configuration?
Question No: 33 ( Marks: 2 )
Where do you find the utility of hardware interrupts in a computer system?
Question No: 34 ( Marks: 2 )
Differentiate between CPU register and Cache Memory.
Question No: 35 ( Marks: 3 )
Name three important schemes that are commonly used for error control.
Question No: 36 ( Marks: 3 )
What do you understand by the term data synchronization ?
Explain briefly the following schemes of data synchronization in your own words
Synchronous transmission
Asynchronous transmission
Question No: 37 ( Marks: 3 )
Differenciate between Spatial Locality And Temporal Locality .
Question No: 38 ( Marks: 5 )
Given a 16-bit parallel output port attached with the FALCON-A CPU as shown in the figure. The
port is mapped onto address DEh of the FALCON-A s I/O space. Sixteen LED branches are
used to display the data being received from the FALCON-A s data bus. Every LED branch is
wired in such a way that when a 1 appears on the particular data bus bit, it turns the LED on; a 0
turns it off.
Which LEDs will be ON when the instruction
out r2, 222
executes on the CPU? Assume r2 contains 1234h.
Question No: 39 ( Marks: 5 )
Consider a 4 way set-associative cache with 256KB capacity and 32 byte lines
a) How many sets are there in the cache?
b) How many bits of address are required to select a set in cache?
Question No: 40 ( Marks: 10 )
Describe the following features of FALCON-A Assembler
Symbol Table
I/O Ports
List File
Single Step
Error Log
Question No: 41 ( Marks: 10 )
How many platters are required for a 40GB disk if there are 1024
bytes/sector, 2048 sectors per track and 4096 tracks per platter
How many platters are required for a 80GB disk if there are 1024
bytes/sector, 2048 sectors per track and 4096 tracks per platter
5 marks question.doc, 80 KB
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